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M61556FP
100 W 1-Channel Amplifier Predriver
REJ03F0089-0100Z Rev.1.0 Sep.19.2003
Description
The M61556FP is a predriver IC developed for use as the output driver of a digital audio power amplifier. It can be combined with an N-channel MOSFET to create a 100 W, 1-channel (8 load) digital amplifier. (The 200 W version, the M61557FP, is pin compatible with the M61556FP.)
Features
* On-chip dead time adjustment circuit: Supports easy adjustment by connecting a single resistor. (H-L dead time can be fine adjusted independently for sides A and B.) * Suitable for driving full-bridge N-channel MOSFET devices. * Maximum bootstrap supply voltage: 88 V (peak value) * Supports high-speed switching. * On-chip diode for bootstrap circuit. * On-chip VDD low voltage detector circuit. * On-chip clock loss detector circuit. * Output impedance: 2.5 * Input is TTL level, allowing connecting to 3.3 V or 5 V processors.
Rev.1.0, Sep.19.2003, page 1 of 13
M61556FP
System Block Diagram (Stereo Configuration)
MCU
INA+
M61556FP
Level shifter
Signal processor LSI for digital amplifier producing PWM output
Dead time generator circuit
(Example) M65817AFP M65881AFP
INB+
Dead time constant current circuit
VDD low voltage detector Clock loss detector
Thermistor detector circuit
Thermistor
External protection detector
Protector control logic
CH1 CH2
Dead time generator circuit
Level shifter
M61556FP
Rev.1.0, Sep.19.2003, page 2 of 13
M61556FP
Sample Application Circuit
GND
VDD = 12V
PowerMOSFET:
1 NC 2 GNDA
0.01F
LSGOUTA 42 NC 41
1F
3 PAD5VA 4 NC 5 INA+ 6 DTCONTA1 7 VDDP
VDDA 40
10
4.7F
NC 39
0.022F 10uH
INA+ INA
HBA 38 HSGOUTA 37
10
M61556FP
NC 36
PROUT PR (protection status monitor)
0.01F
Thermistor
8 PROUT 9 FIL5V 10 NC 11 FILDT
OUTD 35 A DTCON TB1 34 THIN 33 NC 32 PRO TECT 31 DTCON TB2 30 DTCON TB3 29 OUTD 28 B
10
4.7F
0.01F
12 IREFDT
6.2k
External Protect Detector
PowerVDD: Power DD:
13 GNDP 14 NC
Signal processor LSI for digital amplifier producing PWM output
15 DTCONTA2 16 GNDA TA3 DTCON INB+ INB
4.7F
VDDA HSGOUTB 27
0.022uF
CH1 CH2
To other channels
10uH
17 INB+ 18 NC 19 PAD5VB
HBB 26 NC 25 VDDB 24 NC 23 LSGOUTB 22
10 1F
0.01F
20 GNDB 21 NC
Notes :
1. Refer to section 9.1, Dead Time Control, for information on the settings for pins 6, 15, 16, 29, 30, and 34. 2. Audio performance can be improved by connecting a snubber circuit to the output power FET.
Rev.1.0, Sep.19.2003, page 3 of 13
M61556FP
Block diagram
HSGOUTB HSGOUTA LSGOUTA LSGOUTB
22 20
OUTDA
PROTECT
38
37
35 42
33
Thermistor detector circuit
31
26
27
28
Level shifter
Level shifter
Protector control logic
Dead time generate circuit
VDD low voltage detector
IREF
40
3
5
2
7
8
9
11 12
13 24
19
PROUT
FILDT
GNDA
IREFDT
GNDP
VDDA
PAD5VA
VDDP
VDDB
PAD5VB
FIL5V
Level shifter
Dead time generate circuit
Level shifter
17
OUTDB
HBA
THIN
HBB
Rev.1.0, Sep.19.2003, page 4 of 13
GNDB
INA+
INB+
M61556FP
Pin Descriptions
Pin No. Side-A control (pre) block 2 3 5 40 42 35 37 38 6 15 A/B common protectio n block 16 7 8 9 11 12 13 31 Side-B control (pre) block 33 17 19 20 26 27 28 22 24 34 30 29 Pin Name GNDA PADVA INA+ VDDA LSGOUTA OUTDA HSGOUTA HBA DTCONTA1 DTCONTA2 DTCONTA3 VDDP RPOUT FIL5V FILDT IREFDT GNDP PROTECT THIN INB+ PAD5VB GNDB HBB HSGOUTB OUTDB LSGOUTB VDDB DTCONTB1 DTCONTB2 DTCONTB3 Pin Description Ground pin for side-A control circuit Side-A filter pin for generating 5 V power supply on-chip Side-A PWM + input pin (high side) Power supply pin for side-A control circuit Side-A low side prebuffer output Virtual VSS connector pin for side-A high side bootstrap capacitor Side-A high side prebuffer output Bootstrap capacitor connector pin power supply pin for side-A high side. Power is supplied to the high side control circuit from a bootstrap circuit. Pin 1 for adjusting dead time high/low differential Pin 2 for adjusting dead time high/low differential Pin 3 for adjusting dead time high/low differential Power supply pin for common circuit block Protection factor detect output pin. A low-level signal (when pull-up is applied) is output if protection factor is detected (open drain output). Filter pin for generating 5 V power supply on-chip Filter pin for dead time circuit Connector pin for dead time adjustment resistor Ground pin for common circuit block Input pin for external protection control signals Input pin for external thermistor circuit detect voltage Side-B PWM + input pin (high side) Side-B filter pin for generating 5 V power supply on-chip Ground pin for side-B control circuit Bootstrap capacitor connection pin power supply pin for side-B high side. Power is supplied to the high side control circuit from a bootstrap circuit. Side-B high side prebuffer output Virtual VSS connector pin for side-B high side bootstrap capacitor Side-B low side prebuffer output Power supply pin for side-B control circuit Pin 1 for adjusting dead time high/low differential Pin 2 for adjusting dead time high/low differential Pin 3 for adjusting dead time high/low differential
Absolute Maximum Ratings
Parameter HBA, HBB Maximum rated operating voltage Absolute maximum rated voltage Input pin application voltage Internal power consumption Junction temperature Operating temperature range Storage temperature Symbol HBA, HBB VDD Vin Pd Tj Ta Tstg Ratings 88* 16 -0.3 to 5.5 1.1 150 -20 to +75 -40 to +125 Units V V V W C C C Conditions HBA and HBB pin voltage VDD power supply voltage
Note : * HB pin values include peak values for ringing voltage, etc.
Rev.1.0, Sep.19.2003, page 5 of 13
M61556FP
Derating Curve
2.0
Power Dissipation Pd (W)
1.5 1.1 1.0 0.65 0.5
0 0 25 50 75 100 125 150
Ambient temperature Ta (C)
Recommended Operating Condition
Rated value Item Power supply voltage for common circuit and control circuit blocks High input voltage Low input voltage Symbol VDD Min. 10.8 Typ. 12 Max. 13.2 Unit V Condition VDDA (pin 40), VDDB (pin 24) VDDP (pin 7) VIH VIL 2.2 -0.25 5.3 0.8 V V INA+ (pin 5), INB+ (pin 17)
Rev.1.0, Sep.19.2003, page 6 of 13
M61556FP
Electrical characteristics
(Unless otherwise specified, Ta = 25C, VDDP, VDDA, B = 12 V, VDA, B = 21 V)
Limits Item Circuit current VDD circuit current Symbol IDD (A, B) IDDF (A, B) IDDP Input voltage High input voltage Low input voltage Low voltage detection VDD low voltage detect level VDD detect hysteresis voltage Thermistor voltage detection Thermistor voltage detect level Thermistor detect hysteresis voltage Bootstrap diode Diode forward voltage Diode forward voltage Diode operating resistance Low side gain driver High input voltage Low input voltage Pull-up output current Pull-down output current High side gain driver High input voltage Low input voltage Pull-up output current Pull-down output current Switching characteristics Output rise time Output fall time Output rise time (3 V to 9 V) Output fall time (9 V to 3 V) Operation input frequency Minimum input pulse width VFL VFH RDON 1.5 2.0 1.2 TBD TBD TBD V V HB output current = 100A HB output current = 100mA HB output current = 100mA THR THH TBD TBD 6.0 4.8 TBD TBD V V THIN pin (pin 33) Detection Recovery VDDR VDDH TBD TBD 7 0.5 TBD TBD V V Between VDD and GND Detection Recovery VIH VIL 2.2 0.8 V V Min. Typ. 5 30 5 Max. TBD TBD TBD Unit mA mA mA Measuring Conditions No input During operation (f = 768 kHz, duty = 50%) No input
VOLL VOHL IOHL IOLL

0.25 0.25 2 2
0.3 0.3
V V A A
ILO = 100mA ILO = -100mA, VOHL = VDD-VHO VLO = 0V VLO = 12V
VOLH VOHH IOHH IOLH

0.25 0.25 2 2
0.3 0.3
V V A A
IHO = 100mA IHO = -100mA, VOHH = VHB-VHO VHO = 0V VHO = 12V
trc tfc tr tf 1/tpf tpw
TBD 40
TBD TBD TBD TBD 768
TBD TBD TBD
ns ns s s KHz ns
f = 500KHz, CL = 1000pF f = 500KHz, CL = 1000pF f = 50KHz, CL = 0.1F f = 50KHz, CL = 0.1F Cycle = 1.3 s (f = 768 kHz)
Rev.1.0, Sep.19.2003, page 7 of 13
M61556FP
I/O Timing
tpf tpw
INA+,INB+ Td
Dead time
Td
Dead time
HSGOUTA /B LSGOUTA/B
Dead Time To prevent the M61556FP from being destroyed by the shoot-through current from an external MOSFET device, dead time is provided between HSGOUTA and LSGOUTA as well as between HSGOUTB and LSGOUTB. Refer to the Dead Time Control section below for information on adjusting the dead time.
Function
Signal System 1. Dead Time Control Settings The dead time, which protects the M61556FP from being destroyed by the shoot-through current from an external MOSFET device, can be adjusted as desired by the user by adjusting the external resistor (R) connected to pin 12. It is possible to adjust the dead times of the high and low sides by setting the dead time control pins of side-A and sideB to 0 V or 12 V. This makes it easy to tailor the dead time to account for minute variations due to circuit board layout and to match the characteristics of the connected MOSFET devices. Relationship Between Pin 12 Resistor, Dead Time Setting, and Output Shoot-Through Current
Pin 12 Resistance Value Dead time setting Small Short Large Long Small shoot-through current
Output stage shoot-through current Large shoot-through current Note: Dead time values are averages for the high and low sides.
Rev.1.0, Sep.19.2003, page 8 of 13
M61556FP Dead Time Control Pin and High/Low Dead Time Balance
DTCONT*1 12V 12V 12V 12V 0V 0V 0V 0V DTCONT*2 0V 0V 12V 12V 0V 0V 12V 12V DTCONT*3 0V 12V 0V 12V 0V 12V 0V 12V (INIT) INIT (INIT) INIT High Side Dead Time Long Low Side Dead Time Short
Short
Long
Note: The sums of the dead times for the high and low sides produced by the above adjustments are constant.
DTCONT Pin No. list
Side-A Side-B DTCONT*1 Pin 6 Pin 34 DTCONT*2 Pin 15 Pin 30 DTCONT*3 Pin 16 Pin 29 ("INIT" refers to the initial status with no setting made by the user.)
Protection System 2. VDD Low Voltage Detector Circuit In order to prevent internal malfunctioning caused by abnormally low power supply voltage, the M61556FP is equipped with a VDD low voltage detector circuit that is triggered if a drop occurs on the VDD power supply voltage. When abnormally low voltage is detected, a low-level signal is output to the HSGOUTA and HSGOUTB pins and a high-level signal to the LSGOUTA and LSGOUTB pins, the Nch totem pole output is kept low, and a low-level signal, indicating a malfunction, is output to PROUT. (The VDD output circuit is connected to the common power supply VDDP pin (pin 7), so for VDDA and VDDB (pins 24 and 40) an external connection should be made to VDDP.) 3. Clock Loss Detector Circuit The major operation performed by the M61556FP is the input and output of PWM pulse waveforms, so protection is provided to ensure stable bootstrap operation in cases where no signal is input for a set period of time. In the protected state, a low-level signal is output to the HSGOUTA, HSGOUTB, LSGOUTA, and LSGOUTB pins, the high and low sides of the external Nch MOS FET are both turned off, and a low-level signal, indicating a malfunction, is output to PROUT. 4. External Protection Detect Signal Input Pin (PROTECT)* Pin 31 of the M61556FP is the external protection detect signal input pin (PROTECT). If a low-level signal is to pin 31, the on-chip logic circuitry causes a low-level signal to be output to the HSGOUTA, HSGOUTB, LSGOUTA, and LSGOUTB pins, the high and low sides of the external Nch MOS FET to both turn off, and a low-level signal, indicating under protection, to be output to PROUT. 5. External Thermistor Circuit Detect Voltage Input Pin (THIN) Pin 33 of the M61556FP is the external thermistor circuit detect voltage input pin (THIN). If the pin 33 voltage becomes one-half VDD or higher, through resistance division by the external thermistor and resistor, the on-chip logic circuitry causes a low-level signal to be output to the HSGOUTA, HSGOUTB, LSGOUTA, and LSGOUTB pins, the high and low sides of the external Nch MOS FET to both turn off, and a low-level signal, indicating a malfunction, to be output to PROUT.
Rev.1.0, Sep.19.2003, page 9 of 13
M61556FP Overheating Detection Function Diagram
VDD
1/ 2VDD
THIN pin voltage (pin 33) Thermistor
2/ 5VDD
Hys=1.2V (VDD = 12V)
33
THIN
Protection detect output PROUT (pin 8)
INA+ GND
or INB+
Signal output resumes after rising edge detected Signal output pin control
Normal operation Normal operation
Function when malfunction detected
Note: The threshold voltage and hysteresis width are the current setting values, and they can be changed.
Functions When Protection Detection Occurs
When protection detection occurs, a low-level signal is output to the HSGOUTA, HSGOUTB, LSGOUTA, and LSGOUTB pins, asynchronously to the PWM inputs (INA+, INA-, INB+, INB-), the high and low sides of the external Nch MOS FET are both turned off, and a low-level signal, indicating a malfunction, is output to PROUT. The PROUT output and signal output pins states when a malfunction is detected are listed in the table below.
Table of Signal Output Pin States During Protection Operation
PROUT output when malfunction detected VDD low voltage protection Clock loss detection External protection Thermistor L L L L PROTECT input pin L (*) Power transistor output status L Hi-Z Hi-Z Hi-Z
HSGOUTA/B L L L L
LSGOUTA/B H L L L
Recovery from Protection Detection Status
The manner in which recovery to signal output from protection detection status takes place varies depending on the protection circuit involved. Once the recovery conditions have been met, recovery takes place at the rising edge of INA+ or INB+ to high level, whichever is first. The recovery conditions for the different protection functions are listed in the table below.
Rev.1.0, Sep.19.2003, page 10 of 13
M61556FP Necessary Conditions for Recovery from Protection Detection Status
Recovery Conditions External protection* PROTECT pin low: protection status, high: normal operation Recovery: After a rising edge from low to high is input to the PROTECT pin, normal operation resumes at the rising edge of the first signal. If a low-level signal is input to the PROTECT pin, the M61556FP is forced into protected status, regardless of the other modes. After the overheating condition has been corrected and the THIN pin voltage drops to (1/2 VDD - 1.5) V, recovery to normal operation takes place at the rising edge of INA+ or INB+ to high level, whichever is first. After the low voltage condition has been corrected and the on-chip VDD detect circuit determines that the voltage is normal, recovery to normal operation takes place at the rising edge of INA+ or INB+ to high level, whichever is first. After the abnormal input condition has been corrected and the on-chip abnormal input detect circuit determines that the input is normal, recovery to normal operation takes place at the rising edge of INA+ or INB+ to high level, whichever is first.
Thermistor
VDD low voltage detector
Clock loss detector
* Note that the high and low settings are the reverse of those in the old specifications.
External Protection Detect Signal Input Pin PROTECT (Pin 31)/Protection Detect Output PROUT (Pin 9) Timing Diagram
Malfunction identified (external protection) External protection detect signal input pin PROTECT (Pin 31) Protection detect output PROUT (pin 8) Recovery from external protection (rising edge of PROTECT) Should be 1 sec. or more
INA+
or INB+
Signal output recovery after rising edge detection
Signal output pin control
Normal operation
Normal operation
Function when malfunction detected
The above diagram shows the timing from the start of external protection control through recovery from protection status. With the other protection functions, recovery from protected status also occurs when the leading edge is detected, as in the diagram above.
Functions at Power-On
To prevent control malfunctions when the M61556FP is powered on, the logic circuitry determines when VDD has risen to approximately 1.5 V or higher and then outputs a low-level signal to HSGOUTA and HSGOUTB, outputs a high-level signal to LSGOUTA and LSGOUTB, and switches the Nch totem pole output to low-level. This charges the external bootstrap capacitor and ensures stable bootstrap operation.
Rev.1.0, Sep.19.2003, page 11 of 13
M61556FP Power-On Function Diagram
VDD High side HSGOUTA, HSGOUTB (Undefined) Low side LSGOUTA, LSGOUTB Totem pole output OUTDA, OUTDB (Undefined)
1.5V
(OFF)
(ON)
Undefined
"L"
Items in parentheses ( ) indicate the output Nch MOS FET state.
Rev.1.0, Sep.19.2003, page 12 of 13
M61556FP
42P2R-A
JEDEC Code -- e b2
22
MMP
Weight(g) 0.63 Lead Material Alloy 42/Cu Alloy
Plastic 42pin 450mil SSOP
EIAJ Package Code SSOP42-P-450-0.80
Package Dimensions
42
HE
E
L1
L
Rev.1.0, Sep.19.2003, page 13 of 13
e1
F
Recommended Mount Pad
Symbol
21
1
A D
G
A2 y
b
A1
e
A A1 A2 b c D E e HE L L1 z Z1 y c
z Detail G Detail F
Z1
b2 e1 I2
Dimension in Millimeters Min Nom Max 2.4 -- -- -- -- 0.05 -- 2.0 -- 0.5 0.4 0.35 0.2 0.15 0.13 17.7 17.5 17.3 8.6 8.4 8.2 -- 0.8 -- 12.23 11.93 11.63 0.7 0.5 0.3 -- 1.765 -- -- -- 0.75 -- 0.9 -- 0.15 -- -- 0 -- 10 -- 0.5 -- -- 11.43 -- -- 1.27 --
I2
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